Because of the superior properties of silicon as a semiconductor material, it has become the established standard for substrates in the integrated circuit industry. The fabrication of high purity monocrystalline silicon material is well known in the art. Indeed, four-inch and five-inch silicon slices or wafers are commonly used for fabricating thousands of integrated circuits thereon.
The trend is toward the use of larger diameter slices for accommodating a corresponding larger number of integrated circuits. It is preferable to achieve this goal without substantially altering the integrated circuit fabrication processes. However, the use of larger diameter silicon slices is accompanied by several problems.
Aside from the problems in growing or otherwise fabricating six and eight-inch diameter silicon slices, special attention must be directed to the handling of the brittle slices during all fabrication phases to prevent physical damage. Particularly, the larger size silicon slice is more susceptible to fracture or warpage when subjected to the high temperature heating and cooling cycles during integrated circuit fabrication. The temperature gradient generated in silicon slices during heating and cooling causes a hoop stress which can result in crystal damage. Moreover, a warped slice makes subsequent lithography processing difficult, and thus creates a higher probability of unreliable integrated circuits.
During diffusion, oxidation and other integrated circuit fabrication processes, a tray of closely stacked silicon slices is inserted into furnaces at temperatures upwardly of one thousand degrees centigrade. A temperature differential exists radially throughout each silicon slice, the peripherial edges being white hot while the temperature decreases toward the center of the slices. The immediate withdrawal of the silicon slices from the elevated temperature creates severe crystalline stresses within each slice. On many occasions, the crystalline stresses develop into lattice fractures or dislocations, thereby degrading and weakening the slice. Once a dislocation is formed, others tend to agglomerate thereto. It is thus apparent that a single damaged silicon slice may represent the loss of thousands of integrated circuits. While the affects of crystal dislocations are not well understood, there is evidence which indicates that semiconductor junction leakage increases as a result thereof. Also, the dislocations tend to form electron charge generation sites and trap sites.
One approach employed to circumvent the foregoing problems is to slowly insert and withdraw the slices from the furnace in order to prevent a rapid temperature change across the silicon slice. However, to be effective, insertion and withdrawal of the silicon slices must be accomplished over a period ranging up to eighty five minutes. It is apparent that the insertion and withdrawal times are substantial compared with the ten to twenty minutes of actual furnace processing time. The productivity of integrated circuits is thereby diminished.
Another approach taken by those skilled in the art to strengthen silicon semiconductor material is to oxygenate the silicon melt before crystal growth. As a result, oxygen atoms become lodged interstitially between the silicon atoms and create a somewhat hardened material. Oxygenated silicon substrates frequently result in wafer warpage at high temperatures.
From the foregoing, it may be seen that it would be desirable to provide an improved silicon substrate material of increased strength which is less susceptible to breakage or warpage due to lattice dislocations. Such a technique should increase the production yield of integrated circuits formed on such substrates, as well as improve the integrated circuit reliability.